Journal of Radio Electronics. eISSN 1684-1719. 2025. ¹10

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DOI: https://doi.org/10.30898/1684-1719.2025.10.3

 

 

 

STRUCTURE OPTIMIZATION AND CALIBRATION
OF A FREQUENCY SYNTHESIZER WITH A LOW-LEVEL PHASE NOISE
IN THE PHASE-LOCKED LOOP (PLL)

 

V.V. Skulditsky, A.A. Bykadorov, S.V. Melnikov, D.G. Yudin

 

All-Russian Scientific Research Institute “Gradient”
344000, Russia, Rostov-on-Don, Sokolova Avenue, 96

 

The paper was received July 10, 2025.

 

Abstract. The problem of designing a PLL frequency synthesizer with a low level of phase noise is considered. The main technical limits of traditional frequency synthesizer implementations, as well as an analysis and comparison of the known engineering solutions for the structures of designing frequency synthesizers are provided. The structure of a low-noise synthesizer with PLL frequency translation is considered. Two main methods for calibrating a frequency synthesizer in IC with an integrated voltage-controlled oscillator are presented. Useful practical recommendations and an illustrative example are provided.

Key words: frequency synthesizer, phase-locked loop, phase noise, frequency divider, calibration.

Corresponding author: Vladislav Valerievich Skulditsky vladislavskulditsky@yandex.ru

 

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For citation:

Skulditsky V.V., Bykadorov A.A., Melnikov S.V., Yudin D.G. Structure optimization and calibration of a frequency synthesizer with a low-level phase noise in the phase-locked loop (pll). // Journal of Radio Electronics. – 2025. – ¹. 10. https://doi.org/10.30898/1684-1719.2025.10.3 (In Russian)