**Abstract.**
An improved architecture of building a delta-sigma modulator, which is the
basis of fully digital transmitter operating at gigahertz carrier, is presented.
A block diagram of signal processing is represented, a polyphase decomposition of
DSM modulators 1 and 2 orders is carried out. DSM 1 and 2 orders are
implemented in chip Kintex 7 firm Xilinx, using polyphase conception. Logic
optimization is executed for each modulator. The high frequency architecture of
DSM 1 order, which is obtained on optimization, excludes feedback in an
explicit form, has less complexity of combinational logic. The scheme allows to
create logic with 4, 8 and more phases without decreasing clock frequency. The
maximum frequency of realization for standart architecture with 4 phases is
194Mhz, for high frequency architecture with 8 phases – 316Mhz. Optimization
architecture DSM 2 order is made by additional parallelization of calculations
using multiplexer. As
a result, the maximum frequency of the standard architecture for phases 4 is
119 MHz, high-frequency architecture for 4 phases - 223MGts, 8 phases - 134
MHz. The results of the implementation of a polyphase and high-frequency
circuits, including DSM noise, are represented for oversampling ratios 64 and
128.

**Keywords:**
DSM, polyphaser decomposition, high-frequency architecture, OSR.

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