|"JOURNAL OF RADIOELECTRONICS" N 10, 2003|
A Noise Reduction Algorithm Suitable for Hardware Implementation
1 - University of Novi Sad, Faculty of Engeenering, Fruskogorska 11a, 21000 Novi Sad, Serbia & Montenegro, e-mail: firstname.lastname@example.org
2 – Micronas GmbH, Hans Bunte Str. 9, Freiburg, Germany
Received October 29, 2003
In recent years there have been a lot of research and development activities, in both industry and academia, in area of image processing and in noise reduction in particular. However, there is a need for more research efforts in this area because most of the proposed algorithms are to complex for the implementation on embedded platforms, which typically have very limited resources. This paper should be viewed as a contribution to these efforts. In the paper we propose new algorithm and its hardware implementation for the impulse noise reduction filter for the satellite TV picture. This space 2D filter processes the picture in real-time. Its structure is based on median filter and it operates by replacing the noise damaged pixels with values calculated by median filter 3x3. To determine whether a pixel is a noise damaged or not, morphological functions are applied, and because of this the filter was named NMF (New Morphological Filter). The filter equally well reduces the real impulse noise present in a satellite TV picture, in real-time, as it does the salt and paper type of impulse noise. The algorithm hardware implementation was done in FPGA (Field Programming Gate Array) integrated circuit. The NMF’s quality is low mathematical complexity, small demand for hardware resources, a large signal to noise ratio, as well as fine preservation of both edges and tiny details in the filtered picture.
Keywords: Morphological filter, Noise reduction, Satellite TV, Hardware implementation, FPGA, Salt and paper, Image processing, Mathematical complexity